Single-Photon Avalanche Diode theory, simulation, and high performance CMOS integration

Eric Webster

EPSRC Studentship


The main aim of the Ph.D. research project is to quantify SPAD device structure design, through understanding the physics of its operation, in order to engineer improved devices and to perform efficient nano-scale implementation of SPAD technology as part of large scale integrated circuits.

Some specific objectives of the research are to: optimise the wavelength response of CMOS SPADs towards the near infra-red; determine the dimensions, feature geometries, architectures and scaling possibilities for SPAD integration into modern CMOS processes; and to create a quantifiable SPAD design methodology which could be used to optimise SPAD structures for specific applications in either photon counting or time correlated operation.

A specific avenue of investigation is into guard ring design as this is one of the main limiting factors for the geometry shrink of SPADs and has not been thoroughly studied. Guard ring design also poses a potential problem for device shrink because as the active area of the SPAD is reduced, the guard rings could potentially relatively increase in size, or even mitigate the effectiveness of the multiplication region, reducing the overall effectiveness of the device.